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Emanuel Maceira's avatar

This is a sharp and well-curated set of signals — the throughline you’ve identified (from general-purpose compute to purpose-defined compute) is the most important structural shift happening in silicon right now, and it’s playing out at every scale simultaneously.

The Jalapeño chip point deserves more attention than it’s getting. An inference-only ASIC taped out in nine months is a signal about organizational velocity as much as technical capability. What Broadcom and OpenAI demonstrated isn’t just a chip — it’s a new tempo for silicon development that breaks the traditional 3-5 year design cycle. That has cascading implications for everyone who sources compute from general-purpose vendors.

The Korean RISC-V neuromorphic SoC signal is the one I’m watching most carefully from an edge AI perspective. Event-driven compute — where the silicon only activates on meaningful state changes rather than continuously polling — is the architecture that makes always-on edge AI viable for battery-powered and energy-harvesting IoT devices. You can’t run even a small language model on a device that has a 3V coin cell battery unless the idle power profile is essentially zero, and event-driven neuromorphic designs are the closest thing the industry has to that today.

The Huawei Upper 6 GHz / 6G framing matters for edge AI in a specific way: the connectivity layer and the inference layer are converging. As eSIM-equipped edge devices gain reliable low-latency 6G access, the tradeoff between local inference and cloud offload becomes dynamic rather than fixed at design time. Purpose-built silicon for these devices needs to be designed with that hybrid in mind from day one — not bolted on later.

The moat observation at the end is exactly right. The entity that defines the job wins the value. Great edition.

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